The invention relates to methods of making atomic integrated circuit devices and more particularly to methods of making improved, miniaturized atomic semiconductor integrated circuit devices.
1. Field of the Invention
The invention relates to methods of making solid state integrated circuit devices and more particularly to methods of making improved, miniaturized semiconductor integrated circuits devices.
2. Background of the Invention
Shockley, Bardeen, and Brattain invented the transistor around 1950 and started the modern electronics age. Kilby and Noyce next combined active and passive components on a single chip and invented the integrated circuit. But even only several components were combined, the yield was low. Fairchild's Isoplanar technology (FIG. 1) made possible medium-scale and larger-scale integrated circuits in 1972 according to Peltzer's U.S. Pat. No. 3,648,125. Simultaneously, other similar dielectric isolation processes, such as Kooi's LOCOS (i.e., local oxide isolation technology) of Philip and Magdos's oxide-recessed technology of IBM, were also widely used.
In a 1976 four-party Interference No. 98,426, Li for his application Ser. No. 154,300 on round-bottomed isolating oxide groove was considered as the “Senior-most Inventor” having an effective filing date of Sep. 23, 1986 among Fairchild's Peltzer, Philip's Kooi, and IBM's Magdo and Magdo.
According to Peltzer's patent, the Fairchild's Isoplanar device 40 as typified by FIG. 1 in his '125 patent has a n-type epitaxial silicon layer 42 formed on a p-type substrate 41. Oxide isolating regions, e.g., 44a, 44b, 44c and 44d are used to isolate the different components. Each of these oxide isolating regions has a wide central flat bottom each occupying much of the chip real estate and producing unnecessarily larger devices.
Li's round-bottomed isolating oxide groove 21 of FIG. 2 was conceived on September 23, column 12, lines 72–75 1968 as shown in his U.S. Pat. No. 3,585,714, column 12, lines 72–75. In the application Ser. No. 154,300, this device is shown to improve device leakage current and breakdown voltage. Also, the groove bottom G of zero width eliminates the wasted chip real estate of all other existing devices of, e.g., Isoplanar, LOCOS, and oxide-recessed types.
This unique rounding feature not only produces smaller devices, but also give rounded PN junction region peripheral surface minimizing contamination by micron-size or even atomic particles thereby increasing yield. See FIG. 2. The smaller the device size, the more critical this yield factor.
Specifically, the rounded groove 21 produces a curved, exposed peripheral junction surface preventing contamination by rubbing contacts with dust particles. Such contacts form, e.g., metallic shorting paths and drastically reduce the device yield by increasing leakage current and decreasing breakdown voltage. Li's U.S. Pat. No. 3,430,109 discloses at column 5, lines 15–20 that for a one-micron (thick) PN junction region, a single-atomic gold chain on-micron long contains 3,903 gold atoms giving a leakage current of 0.15 ma at 50 volts thereby destroying the device. A single 1-micron gold particle could possibly destroy 7.977×106 particles.
Knowing the problem, the solution is very simple yet critical—groove rounding and the cleaning room. Modern devices have much thinner junction regions so that the same 1-micron gold particle could now destroy over 1 billion devices!
In the patent application Ser. No. 154,300, the device of FIG. 2 is made by thermally growing an oxide groove, band, or material region 21 transversely into a p-type silicon substrate 22. This is followed by oxide-guided, maskless diffusion of n-type dopants from the top surface 23 to give the top n-type silicon layer 24 and the new PN junction region 25. The rounded bottom G has a zero bottom width.
All these devices can still be improved, both in performance and device size. While retaining the rounded bottom feature, the oxide isolating regions or field layers in this present invention are further narrowed down to even one or two atomic layers occupying the minimum chip real estate. The present invention thus provides still better and further miniaturized solid-state integrated circuits (IC) in general and semiconductor integrated circuits in particular.
Specifically, this invention will address the following issues:                1) improving the critical gate layer material and structure;        2) reducing the insulating field oxide region size by orders of magnitude from microns to angstroms;        3) making the entire device more resistant to temperature, stress, impact, vibration, and high-gravity (G) forces due to rapid accelerations and decelerations;        4) simplifying device material inventories and manufacturing process;        5) providing a new type of high-performance flexible circuits;        6) designing 1-D (one-dimensional), 2-D, and 3-D atomic or molecular diode or transistor arrays or IC especially useful for supercomputers and electro-optical telecommunications; and        7) producing new atomic or molecular IC operating selectively in a single-electron, single-hole, single-carrier, or single-photon mode.        
The devices of the invention may use different solid-state or semiconductor materials including Si, Ge, Si—Ge, InP, GaAs, SiC, InAs, InAlP, superconductor, diamond, and periodic group III–V or II–VI semiconductors. In this invention, Si semiconductor materials are exclusively used by way of illustration. Also, metal-oxide-semiconductor (MOS) or, in general, and conductor-insulator-semiconductor (CIS) devices, and single-electron, single-hole, single-carrier, and single-photon IC with silicon dioxide gate and field layers are used exclusively as examples in this specification.
Other types of solid-state devices in general and semiconductor devices in particular can also use this invention. Specifically, electro optical, superconductor, magnetic, ferro electric memory, electrooptomagnetic, single-electron, single-hole, single-carrier, single-photon IC, and other solid-state devices can also be designed according to principles of this invention.
The “heart” of the transistor is the gate dielectric layer, where most electronic actions and the associated heating or degradations occur. The gate oxide dielectric is the smallest but a most critical feature of the transistor. It lies between the transistor's gate electrode, which turns current flow, and the silicon channel through which the current flows. The gate oxide insulates and protects the channel from the gate electrode preventing short circuits. Shrinking this gate oxide layer allows more current out of the switch with less voltage.
More than any other part of the structure, this gate layer determines the device performance and reliability. Many think that this insulating layer would be the limiting factor for producing increasingly smaller chips.
The thickness of gate oxides is the subject of intense research and development worldwide. Bell Laboratory scientists have created a 5-atom silicon dioxide layer that include a 1-atom transition layer between this layer and the substrate. A rapid thermal oxidation technique was used using pure oxygen at 1,000° C. for 10 seconds. Oxides less than 6 angstroms or 3 atoms have been made, but the leakage current was not manageable. Additional reliability issues included adhesion loss, texture, thermally or mechanically induced cracking, moisture adsorption, step coverage, and time-dependent behavior on, e.g., thermal conductivity and breakdown voltage. The reduced mechanical strength is critical in both packaging and processing such as during chemical-mechanical polishing.
Traditionally, the gate dielectric has been—and it still is—a thermally grown layer of silicon dioxide (SiO2) averaged about 25 atoms thick. By continually reducing the gate oxide thickness and the length of the gate electrode, the semiconductor industry has doubled the transistor's switching speed every 18 to 24 months according to the Moore's Law.
This has worked remarkably well, but problems exist. One is that the oxide often permits boron penetration from the gate into the threshold region, degrading the threshold voltage and device performance. The other problem is that as device size shrinks, the gate oxide becomes so thin that “tunneling” currents arise from the gate through the oxide to the substrate, again degrading the device performance.
To overcome the first problem, transistor engineers have developed solutions involving stacked gates and various nitridation techniques. Nitradation adds nitrogen to the silicon dioxide. A successful two-step oxidation/nitridation approach using a sequential in situ steam generation and rapid plasma nitridation process shows a 5–7× reduction in leakage current compared to SiO2 at an effective oxide thickness of less than 20 A (or Angstroms).
The second problem relates to current tunneling through very thin oxides. This problem is more difficult and thought to require a change of materials. The tunneling current rises very quickly as the oxide is thinned down. It is believed that below about 14–15 A, new material must be used to replace the silicon dioxide. One would look for a thinner but defect-free SiO2 film to avoid the excessive leakage current. The new high-k materials must be used in place of the 14–15 A SiO2 layers. Some solutions are possible, but none fit all needs.
The new insulating material must also have the right dielectric constant and be compatible chemically with silicon to get the right interface. Interface micro or atomic engineering may in fact be the key factor that will allow the new or old materials to continue the scaling of field-effect transistors (FET).
The defect-free gate dielectric layer must be put down uniformly in a thin film to tolerate subsequent silicon processing and temperature cycling. There is still no suitable high dielectric constant material and interface layer with the stability and interface characteristics to serve as a gate dielectric.
Metal silicates may be good candidates. Halfnium and zirconium silicates are stable in contact with silicon, between substrate and dielectric. Tantalum pentoxide is also available.
Even with a material other than SiO2, a very thin SiO2 layer will probably still be required at the channel and/or gate electrode interface to preserve interface state characteristics and channel mobility. A major problem with a material other than SiO2 is the probability that a very thin SiO2 layer will still be required at the channel and/or gate electrode interface to preserve interface state characteristics and channel mobility. This would severely reduce any benefits due to the high-k dielectric.
It has been suggested that the first 10 A above the silicon substrate largely determine the leakage properties of the dielectric and the carrier mobilities in the channel underneath. Once past that, only the bulk properties of the film needs to be dealt with. Controlling these properties will be critical to the success of high-k materials. Some hope exists to shrink the silicon dioxide down to 0.1 um (or microns) thick using plasma nitridation to control the first 10 A or so of the dielectric.
The gate material is often a doped poly-silicon with a silicide on top. Interest exists in switching the polysilicon to a metal due to depletion effects associated with the poly. When the device is turned on, the poly-silicon actually depletes a little bit making it look like a thicker oxide. This depletion effect leads to less drive current—a characteristic of a semiconductor material rather than a metal.
The now used high dielectric (k) material is moving from the doped polysilicon to a metal. The advantage of metal gates is that this depletion effect is avoided, and the gate resistance is lowered. However, there are two disadvantages to metal gates. The metal work function of the gate is fixed by the choice of metal. By comparison, the work function in poly-silicon is controllable by varying doping of either n-type or p-type material. This allows optimization of the threshold voltages for both the n-channel and p-channel transistor, not possible with metal.
The main focus of present transistor engineering effort is to maximize the drive current. The present transistor is a current source charging a large capacitor. The higher the current source and the smaller the capacitance, the faster it charges. All the industry's scaling efforts are towards improving the drive current at lower voltages. Second to optimizing drive current is a need to reduce parasitic capacitances at the device levels and the interconnect level. Hence, high-k material for the gate electrode dielectric is moving from doped poly-silicon to a metal.
Sixteen (16) ion implantation steps are commonly used to create the sources and drains for the PMOS and NMOS devices, and the retrograde wells in which they sit. Implantation is also used to dope the gate and to provide the “punch-through stop” pockets. After the implantation, the device must be annealed at a relatively high temperature to remove the implantation damages, to “activate” the dopants, and to insure that all dopant atoms lie exactly where needed.
The junction depth for source/drains should be only 35–70 nm deep for the 100 nm (or 0.1 um) generation due to go into production in 2005. Drain extensions should only be 20–33 nm deep. The abruptness of the source and drain extensions is critical. There are still no known solutions in several areas.
Many believe computer modeling will help researchers determine the optimal doping profile and study the impact of various process parameters on dopant diffusion. A few degrees in temperature can have a significant effect on the doping profiles. Aggressive scaling of the transistor source/drain junction depth requires production worthy (milli-amperes for 300 nm wafers) ion beam current at sub-Kev energies for boron. The requirement for sub-Kev implants is primarily driven by the need to reduce transient enhanced diffusion. Sputtering related dopant loss and other phenomena will most likely preclude the use of sub-Kev implant energies below 0.5 Kev, regardless of available beam current.
Reducing the implant energy, annealing time and dose are of primary importance for achieving the shallowest junctions. Ultra-fast ramp-up rates are of secondary importance—their potential benefit can only be captured with an equally fast ramp-down rate not achievable in today's rapid thermal processing systems. Several combinations of implant and annealing parameters (implant energy, dose, annealing temperature, time and ramp rates) are possible that yield the same junction solutions. It is essential to select solutions which optimize manufacturability.
The semiconductor industry continues to double device functionality every two years or so. It is thought this requires switching to new materials. Instead of aluminum, silicon dioxide and poly-silicon structures, some think that future integrated circuits are thought to be built from copper, low-dielectrics and high-k dielectrics, and “exotic” metals like hafnium and zirconium.
The traditional silicon dioxide insulator needs close thickness control and low defect density. These are thought possible with improved cleaning and oxidation techniques. As the required layer becomes thinner, leakage currents and reliability problems arise. Direct tunneling can occur in very thin layers, giving high leakage current. At 100° C., the maximum voltage rate of a 2.5 nm thick layer of silicon dioxide is only 1.5 v.
A silicon/dual-doped polysilicon gate stack process is used as the mainstay of CMOS device manufacturing since its inception. To replace this process, the new CMOS gate stack process, considered to be the most important film layer in integrated circuits, would require high-k dielectric gate insulator, with a dual metal gate electrode. The use of this new process should be no later than five years. This is generally thought impossible.
A flowable oxide based on hydrogen silsesquioxane is often loused to form ultrathin low-k insulating layers. Use of these layers reduces parasitic capacitance and thus shortens propagation delays. These changes increase by 30% the within-chip processing speed, as compared with other 180 nm CMOS processes.
The use of tungsten instead of aluminum allows fabrication of conductor widths down to 240 nm below the normal metal layers at gate level. The extra routing flexibility achieved by the local interconnect layer enables the silicon area to be reduced by some 10% to 20% in typical core cells. It also permits the spacing between tracks in the first metal layer to be considerably increased, reducing defects in this layer and increasing the yield despite the extra process step.
The traditional silicon dioxide gate insulator presented challenges, such as the need for close thickness control and low defect density. These are thought possible with improved cleaning technology and oxidation techniques. As the required layer becomes thinner, leakage currents and reliability presented problems. Direct tunneling can occur in very thin layers, resulting in high leakage current. At 100° C. the maximum voltage rating of a 2.5 nm thick layer of silicon dioxide is 1.5 V.
High-k dielectrics is one of the major road blocks in device scaling. With extremely smooth gate dielectric and very small channel length, the transistor drive current goes ballistic, increasing the input current flows via the channel from the usual 35% to 85%. The remaining input current collides with the rough edges of the insulating layer.
Low-k polymer dielectrics have been used to replace glass insulators to separate the new copper wires in the new chips. Copper lead wires are also replacing aluminum wires. This material combination will push chip speeds to about one-third faster than today's fastest chips. There are, however, problems to using this system: 1) the plastic is much softer than glass and does not stay in place, making it difficult to make the chips; and 2) these polymers also do not stick to other materials including silicon and other polymers.
Tungsten is replacing aluminum interconnects. The use of tungsten reduces the conductor widths down to 240 nm below the metal layers at gate level. The extra routing flexibility achieved by the local interconnect reduces 10–20% of the silicon area. The spacing between tracks in the first metal layer can be considerably increased to reduce sensitivity of this layer to defects thereby increasing the device yield. However, the very high tungsten density of 19.3 (vs 2.7 for Al, 2.33 for silicon and silicon dioxide) induces deboning from other materials during fast accelerations and decelerations, as shown later.
The capacitance between the gate and channel of an insulated gate FET needs to be high, but in small area devices this cannot be achieved by using a very thin silicon dioxide layer, or the leakage current will be too high, most likely due to material imperfections. A polysilicon gate electrode has been used with germanium doping to control the work function of the material. A variety of metals will be tried as gate electrodes, with TiN/Al or TiN/W being the most likely candidates. Also considered are deposition of high-k gate insulators by the atomic layer chemical vapor deposition technique using aluminum oxide, hafnium oxide, titanium oxide, zirconium oxide, and silicates such as those of zirconium and hafnium.
Ballistic effects occur around the 30 nm channel length when the electrons emitted from the source arrive at the drain without scattering. Small dimensions have great impact on the electrons. The channel lengths of conventional transistors are so long that electrons seldom go all the way from the source to the drain without scattering. But when the channel length gets down to around 35 nm, the ballistic component increases and device performance improves. However, once ballisting occurs, further reduction of the channel length no longer improves the performance. Electrons travel better when the gate oxide is slightly thicker because they are less attracted to the gate directly above the gate oxide layer.
There still is plenty life left in traditional gate structure. Take, for example, the “ballistic nanotransistor”. In these devices, dramatic gains in drive current are possible simply by combining a very smooth gate dielectric with a short channel length, such as in Vertical MOSFET. The main challenge is to replace the traditional silicon dioxide/dual-doped poly-silicon gate stack process. This process has been the mainstay of CMOS device manufacturing since its inception. The new CMOS gate stack process will require the cost-effective, low-temperature integration of nanometer scale high-k dielectric gate insulators, with dual metal gate electrodes. The replacement should be within five years. History has shown, however, that changes of this magnitude normally require ten years or more to implement.
The very slow process in finding new semiconoductor materials is looming as a grand challenge in chip design. There are still many, many problems that are material-limited particularly for new improved devices. New material selection, design, and processing methods must be found and made. The whole manufacturing process is generally too complicated involving, e.g., too many materials and equipment to achieve high repeatability and good device yield, performance, and repeatability. Most of the materials are not applied in optimal ways. This invention will address many of these issues.